There is a constant drive within the semiconductor industry to increase overall performance and operating speed of integrated circuit devices, e.g., microprocessors, memory devices, communication chips, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices and the components that make up such devices, e.g., transistors. That is, many features of a typical field effect transistor (FET), e.g., channel length, junction depth, gate dielectric thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase device performance and the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
In addition, there is a constant drive to increase the density of modern integrated circuit devices, i.e., to put more and more semiconductor devices, e.g., transistors, closer together on a single chip. Increasing the density of integrated circuit devices makes more efficient use of the semiconductor die area, and may assist in increasing the overall yield from semiconductor manufacturing operations.
One problem encountered in efforts to increase the density of modern integrated circuit devices arises in forming ever smaller critical dimension features. Typically, a polysilicon feature such as a transistor gate structure is formed by depositing a polysilicon layer over a substrate, followed by forming a photoresist layer over the polysilicon. The photoresist is then selectively exposed to ultraviolet radiation, and (in the cases of a positive photoresist) the exposed portions are removed by application of a developer solution. The patterned photoresist is then subsequently employed as an etch mask in patterning the underlying polysilicon.
One challenge in reducing the critical dimension of a polysilicon feature is line edge roughness (LER) of the developed photoresist, which then gets transferred down to the polysilicon during the subsequent etching. It is desirable to reduce line edge roughness to improve feature dimension control as scaling continues.